The subject matter disclosed herein is concerned with semiconductor memory devices. In particular, the subject matter disclosed herein relates to technologies for repairing defective cells and trimming voltages in a flash memory device.
Improvements in semiconductor memory devices to increase performance include higher integration density, larger capacity, and increased sizes of chips. However, these improvements may impose particular requirements and may result in various problems. Such requirements and problems may include decreased product yields, narrower line widths, increased processing steps, more complicated fabrication techniques, and so forth. As a result, semiconductor memory devices are designed with spare memory cells (or redundant memory cells) to substitute for defective memory cells. Semiconductor memory devices usually include fuse boxes so that addresses of defective cells are substituted with the addresses of redundant memory cells. After the detection of defective cells by test operations, addresses of the defective cells are assigned to corresponding redundant cells through a programming process by cutting fuses in the fuse box. Although a given semiconductor memory chip may have defective cells, the chip may still be used as a good product by replacing the defective cells with redundant cells. However, if there are more defective cells than redundant cells, the semiconductor memory chip is defined as a failure, because it is impossible to repair all of the defective cells.
Furthermore, semiconductor memory devices may utilize internal power sources having various DC voltage levels. Those DC voltages are supplied by voltage generators embedded in the semiconductor memory devices. The levels of DC voltages are determined when designing the semiconductor memory devices. For the optimum memory operations, the reference voltages should to be supplied from the voltage generators at the designed voltage level. However, reference voltages generated in the memory devices during actual operation may not be equal with the designed levels due to various factors involved in manufacturing processes. When the difference between the designed and actual reference voltage is greater than a predetermined value, the difference may be corrected using a fuse box for trimming the DC voltage levels on the reference. An optimum DC voltage is properly selected by programming fuses of the fuse box connected to the internal voltage generator. In the fuse box, the fuses are selectively cut to select an optimum level among various available voltages.
However, there are problems associated with using a fuse box for repairing defective cells and trimming DC voltages. Additional processing steps are needed for the fuse programming operation in the fuse box. In addition, chip integration density is restricted due to the additional circuit area for the fuse box. Furthermore, it is difficult if not impossible to repair the semiconductor memory chip from progressive defects occurring after packaging of the chip or changes due to the operating environment of the chip.